In recent years, when semiconductor devices or various devices used in a digital communication system whose communication rate has increased to a gigahertz frequency band are tested, it is necessary to supply a bias voltage (offset voltage) corresponding to the input interface of a device under test, which is a device to be tested, to a high-speed digital signal.
The inventors have proposed a digital signal offset adjustment device that applies a bias voltage which is an arbitrary DC voltage to a digital signal and outputs the digital signal, as disclosed in the following Patent Document 1.
As illustrated in FIG. 3, a digital signal offset adjustment device 101 disclosed in Patent Document 1 includes an input terminal 102 to which a digital input signal that has broadband frequency characteristics including a low-frequency component, a DC component, and a high-frequency component is input, a DC voltage generator 104 that outputs a desired DC bias voltage set by a bias voltage setting unit 103, an output terminal 105 for outputting a digital output signal obtained by adding the DC bias voltage output from the DC voltage generator 104 to the low-frequency component, the DC component, and the high-frequency component of the digital input signal input to the input terminal 102, a capacitor 106 that is connected between the input terminal 102 and the output terminal 105 and passes the high-frequency component of the digital input signal input to the input terminal 102 to the output terminal 105, a first coil 107 that has one end connected to the input terminal 102 and passes the low-frequency component and the DC component of the digital input signal to the other end, a second coil 108 that has one end connected to the output terminal 105, and a synthetic circuit 109 that has a first input end connected to the other end of the first coil 107, synthesizes the low-frequency component and the DC component of the digital input signal which is input to the first input end through the other end of the first coil 107 with the DC bias voltage (offset voltage) output from the DC voltage generator 104 and outputs the synthesized signal from an output end to the output terminal 105 through the other end of the second coil 108. In addition, the synthetic circuit 109 includes a frequency characteristic compensation circuit 109a that compensates for frequency characteristics such that the gain of an operational amplifier increases as the frequency of the low-frequency component in the digital input signal output from the other end of the first coil 107 increases.
The digital signal offset adjustment device 101 includes the frequency characteristic compensation circuit 109a having the characteristic that the gain increases as the frequency of an AC component in the signal output from the other end of the first coil 107 increases. Therefore, it is possible to accurately transmit a broadband digital signal including a low-frequency component to a high-frequency component in a frequency band of several hundreds of hertz to several gigahertz, without any waveform distortion, and to appropriately test various devices used in the digital communication system.
The inventors have proposed a digital signal offset adjustment device disclosed in the following Patent Document 2 as an improvement of the digital signal offset adjustment device 101 disclosed in the above-mentioned Patent Document 1.
The digital signal offset adjustment device disclosed in Patent Document 2 includes an isolation circuit that is provided between the capacitor 106 and the output terminal 105, in addition to the structure illustrated in FIG. 3. An AC component of a digital input signal input to the input terminal 102 is transmitted to the output terminal 105 through the capacitor 106 and the isolation circuit. A DC component and a low-frequency component are extracted by the first coil 107 and are synthesized with a DC bias signal and the synthesized signal is supplied to the output terminal 105 through the second coil 108. In addition, the isolation circuit prevents the reverse flow of the low-frequency component to the input terminal 102. Therefore, it is possible to transmit a broadband waveform with low distortion, without being affected by a circuit connected to the output side, for example, without returning a reflected signal caused by mismatching to the input side.
Each of the isolation circuit and the synthetic circuit 109 includes a variable-gain amplifier. The digital signal offset adjustment device includes amplitude control means for controlling the variable-gain amplifier of each of the isolation circuit and the synthetic circuit 109 such that a digital signal with a designated amplitude value is output from the output terminal 105. Therefore, it is possible to apply an arbitrary DC offset to the digital signal to be output and to arbitrarily set the amplitude of the digital signal.